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SoC Platform Engineer

Job in Saratoga, Santa Clara County, California, 95071, USA
Listing for: Medium
Full Time position
Listed on 2026-07-27
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 220000 USD Yearly USD 150000.00 220000.00 YEAR
Job Description & How to Apply Below

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

What you will do:
  • IP Integration and Verification

    · IP Integration:
    Evaluate, integrate, and verify IP blocks within the SoC, ensuring correct connectivity, configuration, and interoperability across the platform.

    · Feature and Module Firmware:
    Author targeted test firmware to bring up and verify individual IP blocks and hardware features at the module level.

    · Subsystem Firmware:
    Develop subsystem-level test firmware to validate interactions between integrated components and confirm correct system behavior across hardware boundaries.

    Testbench Development and Build Flows

    · Testbench Infrastructure:
    Define, implement, and maintain system-level test benches covering subsystem and full SoC verification scenarios.

    · Build Flow Management:
    Own and manage testbench build flows, ensuring reproducibility, scalability, and integration with the broader verification environment.

    SoC Feature Implementation

    · Hardware Security:
    Implement SoC-level security features, including secure boot, hardware root of trust, and cryptographic accelerator integration.

    · Inter-Subsystem Communication:
    Define and implement communication fabrics and protocols between SoC subsystems, including AMBA-based interconnects (AXI, AHB, APB).

    · Power Management:
    Implement hardware power management features, including power domain control, clock gating, and low-power state transitions.

    · Boot Flow and Configuration:
    Define and implement the SoC boot architecture, including reset sequencing, configuration registers, and boot ROM integration.

What you bring to this role:

  • · Hardware Description Languages

    :
    Proficiency in RTL design and verification using System Verilog and/or VHDL.


    · Verification Methodologies

    :
    Experience with UVM or similar structured verification methodologies.


    · Firmware Development

    :
    Ability to write bare-metal C firmware for hardware bring-up, feature validation, and test automation on embedded targets.


    · AMBA Interconnects

    :
    Strong knowledge of AMBA protocols (AXI, AHB, APB) and their application in SoC integration.


    · SoC Architecture

    :
    Understanding of SoC subsystem partitioning, memory maps, interrupt routing, and hardware/software interfaces.


    · Debugging Tools

    :
    Experience with simulation tools (e.g., VCS, Questa, Xcelium) and hardware debug environments (JTAG, logic analyzers, oscilloscopes).


    · Scripting

    :
    Proficiency in scripting languages such as Python, Tcl, Bash, and Makefiles for build flow automation and test infrastructure.


    · Version Control

    :
    Expertise with Git or similar version control systems.

Bonus points for the following:
  • · Experience with ARM Corstone reference designs and Cortex-M or Cortex-A processor integration.

    · Familiarity with Trusted Firmware-M, MCUboot, or PSA-certified security architectures.

    · Knowledge of embedded security concepts, including cryptographic algorithms and Post-Quantum Cryptography (PQC).

    · Experience with formal verification or property checking tools.

    · Familiarity with Cortex-A and Cortex-M class processors, NPU processors, and DSP processors.

    · Familiarity with FPGA emulation platforms for pre-silicon validation.

    · Knowledge of 3

    GPP network protocols as they relate to SoC modem or connectivity subsystem integration.

    · Experience with low-power SoC design and power intent methodologies (UPF/CPF).

    ·

    Education:

    Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Collaboration and Documentation:

  • · Cross-Functional Partnership

    :
    Work closely with SoC…

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