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Senior DV Engineer LEO Satellite ASIC Verification
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-07-27
Listing for:
Medium
Full Time
position Listed on 2026-07-27
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
E-Space is seeking a Digital Design Verification Engineer to verify our custom ASICs for satellite and wireless telephony. Candidates should be proficient in Verilog, System Verilog, and UVM, with knowledge of C/C++ for verification and scripting in Perl or Python.
Leadership in verification at the block level is a plus for this role based in Saratoga, CA. We expect 6+ years of design verification experience in the semiconductor industry and offer a competitive base pay with total compensation
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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