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Senior DFT Architect - Multi-Chip SoC
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-08-21
Listing for:
Eridu Corporation
Full Time
position Listed on 2026-08-21
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer
Job Description & How to Apply Below
Eridu, a Silicon Valley hardware startup, seeks an experienced engineer to define the DFT architecture for a multi-chip SOC, covering test design, SDC constraints, and ATPG. You will work with RTL and gate-level simulations and oversee high-coverage scan techniques, including LBIST and streaming.
Expertise with Mentor/Synopsys test tools is preferred. Based in Saratoga, CA, the role offers a base salary in the range of 195,000–250,000 USD per year, with compensation determined by skills and
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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