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Senior DFT Architect - Multi-Chip SOC
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-08-22
Listing for:
Eridu Corp.
Full Time
position Listed on 2026-08-22
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Eridu Corp., a Silicon Valley hardware startup, seeks a senior EE to define the DFT architecture for a multi-chip SOC, encompassing test design functions such as Scan, BIST, Memory Repair, and advanced DFT techniques.
You will work with a world-class engineering team, require 15+ years of EE experience, fluency in Verilog/System Verilog, RTL and gate-level simulation, and proficiency with Mentor or Synopsys test tools. The role is based in Saratoga, CA with a competitive base salary.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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