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DFT Architect for Multi-Chip AI SOCs
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-08-22
Listing for:
Eridu
Full Time
position Listed on 2026-08-22
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Eridu, a Silicon Valley-based hardware startup, seeks a senior DFT/ASIC engineer to shape the DFT architecture for a multi-chip SOC. You will work on synthesis constraints, LBIST, and advanced test methods in a fast-paced team.
You will apply Verilog/System Verilog, deep sub-micron 7nm processes, and EMIB-aware designs to improve test coverage, power, and performance while collaborating across design and verification teams in Saratoga, CA.
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