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RTL Design Engineer
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-09-04
Listing for:
InterSources Inc
Full Time
position Listed on 2026-09-04
Job specializations:
-
Engineering
Systems Engineer, Test Engineer, Hardware Engineer
Job Description & How to Apply Below
- ME/BE with a minimum of 8-15 years of experience.
- Hands-on knowledge of System Verilog and Verilog is mandatory.
- Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
- Proven expertise in designing and optimizing scheduling and QoS mechanisms.
- Experience with Ethernet and IP protocols.
- Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
- Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
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