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Senior RTL Design Engineer - ASIC, SystemVerilog & QoS
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-09-04
Listing for:
InterSources Inc
Full Time
position Listed on 2026-09-04
Job specializations:
-
Engineering
Hardware Engineer
Job Description & How to Apply Below
Inter Sources Inc. is seeking a senior engineer with 8–15 years of ME/BE experience to design and optimize ASIC-related systems.
The role requires hands-on System Verilog/Verilog, in-depth knowledge of ASIC methodologies, and strong analytical skills for debugging complex networking issues. The candidate should be proficient in enabling high-performance scheduling and QoS mechanisms, with experience in Ethernet and IP protocols and a proven ability to communicate effectively within
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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