Substrate Layout Design Engineer

About this position
About Eridu

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference.

We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company).

The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the‑art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

We are seeking an experienced Substrate Layout Design Engineer to own the physical layout and routing of large, high-density, multi-die organic packages and modules, and their associated high-speed interface boards. The role spans early routing feasibility through manufacturing release and includes high-speed serial interfaces, clock and control signals, and high-current power delivery within demanding electrical, mechanical, and fabrication constraints.

The successful candidate will work closely with package integration, ASIC, signal integrity, power integrity, mechanical, system, and manufacturing teams. This position requires strong hands‑on layout capability, sound engineering judgment, and the ability to work directly with foundry, substrate, assembly, board‑fabrication, and contract manufacturing partners.

• Own end‑to‑end physical layout of advanced organic substrates using Siemens Xpedition, Cadence Allegro, including die and component placement, bump map and netlist alignment, escape and breakout routing, via planning, reference planes, and layer stack‑up implementation.
• Perform early routing‑feasibility studies using die floor plans, I/O placement, package and board interfaces, mechanical keep‑out zones, manufacturing rules, and system level constraints; identify bottlenecks and recommend floorplan, bump map, or stack‑up changes.
• Implement high speed serial and differential routing with controlled impedance, length and skew management, crosstalk control, via‑transition optimization, and continuous return paths in accordance with SI requirements.
• Route clock, control, management, and other low‑speed interfaces while meeting topology, shielding, isolation, and reference plane requirements.
• Develop robust power and ground distribution for high power devices and voltage regulation interfaces, including plane allocation, current density management, via arrays, and implementation of PI constraints.
• Support package‑to‑board co‑design and layout of high speed interface boards, including connector and component placement, signal breakout, power delivery, and mechanical alignment with the package or module.
• Integrate fine pitch interconnect regions and embedded or integrated passive structures…