ASIC Architect

About Eridu

Eridu is a Silicon Valley-based hardware startup that accelerates AI data centers.

We are looking for a highly experienced ASIC Architect to contribute to the definition and implementation of Eridu's industry-leading networking products. This is a unique opportunity to help shape the future of AI networking.

• Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications.
• Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency.
• Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies.
• Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff.
• Guide integration of internal and external IPs (e.g., MAC, PCIe, Ser Des) into the broader architecture and drive interface requirements.
• Participate in design reviews, performance modeling, test and verification strategies and architectural trade‑off analysis.
• Contribute to post-silicon validation for performance and correctness, and investigate and resolve complex issues related to ASIC data path, working closely with cross‑functional teams including hardware engineers, firmware developers, and system architects.

• MSEE with 10+ years of experience, preferably in networking ASIC architecture and design.
• Experience in related areas of computer and parallel processing architectures—particularly complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths.
• Deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert.
• Demonstrated expertise in microarchitecture definition, performance modeling, and trade‑off analysis; capability to develop architecture behavioral models.
• Experience working across the ASIC development lifecycle, from concept through productization.
• Experience in high‑speed I/O integration (e.g., PCIe Gen5/Gen6, Ser Des) and Software Control Plane interface architecture.
• Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power).
• Strong analytical and problem‑solving abilities, with meticulous attention to detail in troubleshooting and debugging complex issues; exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly.

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

210, USD per year (San Francisco, Bay Area)