Software Engineer Speed SerDes

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference.

We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co‑founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro‑LED company).

The company is in execution mode and has a world‑class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

We are seeking a highly experienced Ser Des software engineer to lead the development, bring‑up, validation, and optimization of next‑generation high‑speed interfaces. The successful candidate will work with 224 Gb/s-per‑lane Ethernet Ser Des , PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon.

This is a senior technical role requiring strong knowledge of Ser Des architecture, PHY initialization, link training, equalization, calibration, diagnostics, and system‑level signal‑integrity behavior. The engineer will work closely with analog and mixed‑signal designers, ASIC architects, firmware teams, validation engineers, board designers, and system software developers.

• Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed
  
  SerDesPHYs.
• Lead bring‑up and optimization of 224G PAM4
  
  Ser Desused in Ethernet switch, networking, and accelerator products.
• Develop software support for PCIe Ser Des , including link initialization, training, equalization, lane management, error recovery, and diagnostics.
• Develop software support for UCIe die‑to‑die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis.
• Implement Ser Desadaptation  and calibration workflows, including:
• Transmitter amplitude, pre‑cursor, and post‑cursor tuning
• Receiver CTLE, VGA, DFE, and CDR configuration
• Eye optimization and margining
• Polarity inversion and lane remapping
• Background calibration and environmental compensation
• Develop APIs, drivers, firmware interfaces, command‑line tools, and diagnostic utilities forSerDescontrol.
• Support Ethernet auto‑negotiation and link training, including Clause 73 and Clause 72/136–related workflows where applicable.
• Support PCIe LTSSM interaction, preset and coefficient negotiation, lane margining, retraining, and recovery.
• Support UCIe link state management, PHY repair mechanisms, sideband interactions, and link reliability features.
• Create automated characterization and production‑test software for:
• PRBS generation and checking
• BER measurement
• Eye scans and bathtub curves
• Jitter and signal‑margin analysis
• Loopback testing
• Lane failure isolation
• Channel and package characterization
• Analyze difficult…