RTL Design Engineer

Overview

Role: ASIC Frontend Digital Implementation Engineer

Location:
Atlanta GA (Onsite)

Job Type: C2C

Interview: 2 rounds of virtual interview

• Executes the digital logic synthesis, DFT insertion, PNR team support, and signoff for multiple Synaptics design partitions.
• Implement and iterate on SDC timing constraints to meet timing requirements for each partition.
• Utilize existing in-house frontend digital implementation flows based on Synopsys (Design Compiler, Formality, Primetime) and Siemens (Tessent) EDA tools for above tasks.
• Perform iterations of various levels of design and timing quality for each digital partition with support from internal RTL team and external backend PNR vendor.
• Meet internal quality metrics for each iteration, with final one being foundry required signoff quality for tapeout in Dec 2026.

• Experience with Digital Implementation Tools from Synopsys, Cadence, and/or Siemens EDA vendors.
• Candidates with 10 years implementation experience are ideal, but Synaptics would also consider