Advanced ASIC FPGA Design Engineer Crypto and Cross Domain Solutions

Advanced Asic Fpga Design Engineer For Crypto And Cross Domain Solutions

Architect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families.

Perform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming, floor planning, and physical optimization.

Develop and execute block-level simulations using Questa Sim/Model Sim with code coverage analysis (statement, branch, condition, expression).

Create self-checking test benches for correctness verification.

Design high-speed interfaces for inter-module communication and system integration.

Collaborate with systems engineers, software developers, and verification engineers in an Agile development environment.

Participate in design reviews, peer code reviews, and documentation of design specifications and interface control documents.

Contribute to CI/CD pipeline development for automated synthesis, simulation regression, and coverage tracking.

Support integration and lab bring-up activities, including on-target FPGA debug using ILAs and JTAG-based tools.

• Strong proficiency in VHDL and/or Verilog/System Verilog for synthesizable RTL design
• Hands-on experience with Xilinx Vivado Design Suite or Microchip Libero for synthesis, implementation, and timing analysis
• Experience targeting Xilinx and Microchip device families
• Ability to achieve timing closure on designs at 300+ MHz clock rates
• Experience with FPGA simulation tools (Questa Sim or Model Sim)
• Proficiency in writing self-checking test benches with automated pass/fail determination
• Understanding of high-speed digital design principles: pipelining, clock domain crossing (CDC), metastability mitigation, and synchronous design
• Experience with AXI-Stream, AXI4, or similar on-chip bus protocols
• Ability to read and interpret timing reports, utilization summaries, and critical-path analysis output
• Strong written and verbal communication skills for design documentation and technical presentations
• U.S. Citizenship and ability to obtain/maintain a Secret security clearance

• Experience with cryptographic algorithm implementation in hardware (AES, GCM, SHA, ECC, RSA, or similar)
• Experience with high-speed serial interfaces: PCIe, Ethernet (10G/25G/100G), Fibre Channel, Aurora, or GTY/GTM transceivers
• Experience with CI/CD pipelines for FPGA development (Git Lab CI) including automated synthesis and regression testing
• Proficiency in scripting languages (Tcl, Python, Bash) for build automation and design flow scripting
• Experience with version control systems (Git Lab) and collaborative development workflows
• Experience with Xilinx IP cores: FIFO Generator, Clock Wizard, MIG/DDR controllers, DMA/Bridge subsystems
• Experience with embedded processors in FPGA (Micro Blaze, Zynq PS, Versal AI Engine)