Digital Design Engineer

Renesas Electronics is seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications.

• Interpret high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
• Support full product lifecycle from concept to mass‑production; communicating closely with wider organization through the various stages of silicon development.
• Provide technical leadership & influence to the digital design team by contributing to technical discussions & reviews, mentoring junior engineers, and supporting recruitment.
• Work closely with Analog and Verification engineers to deliver high‑quality silicon solutions.

• Ensure digital development process is state‑of‑the‑art and achieves budget, schedule, and project deliverable goals.
• Design digital RTL that meets timing, area, power and any adhering standards specifications.
• Integrate design at the top level and run block & top‑level simulations.
• Participate in all aspects of mixed‑signal design flow – micro‑architecture, design partitioning, RTL Verilog/System Verilog design, generating timing constraints, synthesis, interaction with P&R team, timing analysis, LINT, CDC, RDC, UPF.
• Work closely with P&R team to generate a layout that meets timing, area, and power requirements.
• Support DFT strategy and implementation, and review test case development.
• Assist with top‑level test‑bench debug and run RTL & gate‑level simulations.
• Collaborate with analog and digital verification engineers to develop complex test scenarios for pre‑silicon verification.
• Support analog team to develop AMS, System Verilog or Verilog‑real behavioral models.
• Develop detailed block & chip‑level design documents and collateral.
• Hold and participate in key design reviews and complete various checklists.
• Perform silicon evaluation as required.
• Document device errata, develop work‑around solutions, and implement engineering changes when necessary.

• More than 10 years of digital design experience in wireless handheld, data conversion, and power management.
• Degree‑level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
• Fluent in Verilog/System Verilog RTL for digital CMOS circuit design.
• Strong understanding of ASIC design methodology.
• Strong understanding of Lint, CDC & RDC tools.
• Strong understanding of block‑level & chip‑level verification techniques.
• Strong & proven ability to debug both RTL & gate‑level simulations.
• Mandatory competence in written and verbal English.
• Willingness to travel domestically or internationally on short notice.
• Ability to work independently and collaboratively.
• Preferred: experience with Digital Signal Processing (DSP) concepts and hardware realizations.
• Preferred: experience with methodology and flow automation using appropriate scripting.
• Preferred: experience with mixed‑signal design methodologies.
• Preferred: experience developing design constraints and hand‑off to P&R.
• Preferred: experience with STA and timing closure.
• Preferred: experience with low‑power design techniques, including clock and power gating (UPF).
• Preferred: experience with power analysis and optimization.
• Preferred: experience with advanced verification methodologies (UVM).
• Preferred: experience with industry‑standard protocols such as AMBA or I2C.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.