Sr DSP​/RTL Engineer

The Role

We’re looking for a Senior DSP / RTL Engineer who can own both the signal processing algorithms and their efficient digital implementation for our phased array solutions. As one of our early senior digital hires, you will define processing architecture, develop beamforming and adaptive algorithms, and implement key blocks in RTL—bridging the gap from concept to silicon/FPGA.

You’ll work end-to-end: algorithm design and modeling, fixed-point conversion, RTL coding and synthesis, timing closure, and lab validation. The decisions you make will directly shape system capability and product differentiation.

• Develop and refine DSP algorithms for digital beamforming, adaptive nulling, channel estimation, calibration, and interference mitigation in communications and radar phased arrays

• Own algorithm architecture from high-level floating-point models (MATLAB/Python) through fixed-point design, quantization analysis, and bit-true modeling

• Design and implement digital RTL (System Verilog/Verilog) for DSP datapaths, control logic, beamforming engines, high-speed interfaces, and supporting blocks

• Drive RTL designs through synthesis, timing analysis, lint/CDC checks, place-and-route support, and silicon/FPGA validation

• Define performance requirements and hardware architecture trade-offs (throughput, latency, area, power); optimize implementations for efficient resource utilization

• Perform system-level simulations and link analyses to quantify algorithm and implementation impact on overall array performance (SINR, EVM, detection range, etc.)

• Support lab bring‑up, debug, and iterative refinement of algorithms and RTL on FPGA/ASIC prototypes based on measured data

• Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field

• 7–10 years of relevant experience spanning digital signal processing algorithm development and digital RTL design for ASICs or FPGAs

• Strong proficiency with MATLAB and/or Python for algorithm design, simulation, and fixed‑point analysis

• Proven hands‑on experience writing production‑quality System Verilog/Verilog RTL, including synthesis, timing closure, lint, and CDC analysis

• Solid foundation in DSP fundamentals: multi‑rate processing, adaptive filtering, array signal processing, estimation theory, and numerical considerations for fixed‑point arithmetic

• Demonstrated ability to translate algorithms into efficient real‑time hardware implementations

• MSc or PhD with a focus on signal processing, communications, VLSI, or radar systems

• Direct experience with digital beamforming, adaptive arrays, MIMO processing, or space‑time adaptive processing (STAP)

• Background in communications (e.g., 5G/6G, satellite) or radar system requirements and performance metrics

• Experience taking designs from algorithm through RTL, synthesis, timing closure, and post‑silicon or FPGA validation

• Familiarity with high‑speed interfaces, AXI/APB buses, low‑power design techniques, and industry‑standard EDA tools (Cadence/Synopsys)

• Prior work on phased‑array or multi‑antenna systems from concept through fielded product

This is a rare ground‑floor opportunity. Joining a startup at this stage means your work has a direct, visible effect on whether the company succeeds—and a corresponding upside as we grow. Because we build the entire system in‑house, you’ll see your algorithms and RTL designs integrated into real phased arrays and deployed in working systems, not handed off and forgotten. You’ll have real ownership and a seat at the table on technical direction.

This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.