Senior ASIC Emulation Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles. This is a hands‑on role with high ownership, deep technical engagement, and the opportunity to shape first‑generation silicon and system methodology.

• Build, integrate, and maintain full-chip, multi-chips and system-levelemulationmodels on platforms such as Palladium, ZeBu, or Veloce.
• Define and evolveemulationstrategy, methodology, and workflows across the ASIC organization.
• Work with RTL engineers to compile, map, and optimize designs foretulationperformance, capacity, and stability.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
• Support system‑level testing inemulationby enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end‑to‑end workloads.
• Accelerate overall verification throughput by helping DV team run targeted and high‑value tests inemulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
• Enable firmware, boot loader, driver, and software teams by providing robustemulationplatforms and assisting in HW/SW integration debug.
• Runemulationworkloads, triage failures, perform root‑cause analysis, and collaborate across design and verification to resolve issues.
• Maintain and enhance automation for compile flows, regression management, and continuous integration.
• Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulationbest practices.
• Support silicon bring‑up and post‑silicon validation through test reuse, diagnostics, and pre/post‑silicon correlation.
• Manage interactions with external IP providers oremulationpartners when needed.

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC development, focused on emulation
• Solid understanding of System Verilog, digital logic, RTL flows, DV methodologies, and ASIC development life cycles.
• Hands‑on expertise with majoremulationplatforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
• Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
• Experience with hardware/software interfaces, embedded processors, firmware bring‑up, and C/C++‑based system‑level testing.
• Familiarity with industry‑standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
• Experience driving cross‑functional debug involving RTL, DV, firmware,…