Senior -Speed PCB Engineer - TeraWave

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based communications with Tera Wave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

• Lead the physical design of complex, multi-layer PCBs for the Tera Wave network switch platform.
• Perform pre- and post-layout signal integrity (SI) analysis, including Ser Des lanes, DDR memory buses, and high-density Ethernet switch interconnects.
• Apply advanced PCB design techniques including:
  • Controlled impedance routing
    for differential pairs and single-ended high-speed signals.
  • Via structures
    to minimize stub lengths and optimize signal path routing in high-density designs.
  • Dielectric material - understanding how material affects differential pair skew and impedance variation and applying strategies.
• Define and review PCB layer stack-ups in collaboration with PCB fabricators, specifying laminate materials, prepreg selection, copper weights, and via structures to meet SI, power integrity, and manufacturing reliability and yield requirements including coupon testing.
• Develop and execute full 3D electromagnetic (EM) simulation models of critical PCB structures extracting broadband S-parameter models that capture frequency-dependent losses, reflections, and crosstalk without reliance on simplified lumped element approximations.
• Perform SI simulation to validate eye margins, crosstalk levels, and model accuracy versus physical measurement.
• Apply de-embedding techniques and use VNA measurements and TDR analysis to correlate simulated SI results with physical hardware measurements.

• Design DDR4, and/or DDR5 memory subsystems with a thorough understanding of fly-by topology, write leveling, read/write training, and the constraints imposed by the memory controller.
• Understand and account for the PCB routing limitations of processor and microcontroller memory interfaces, including:
  • Byte lane grouping and skew budgets within and across DQ groups.
  • Address/command bus fly-by routing and stub minimization.
  • Reference plane continuity and return current management beneath DDR routing fields.
  • PCB trace length matching requirements relative to clock and strobe signals.
• Demonstrate DDR compliance through laboratory measurements.

• Design PCB layouts for high-speed serializer/deserializer (Ser Des) interfaces including 10
  
  GbE, 25
  
  GbE, 40
  
  GbE, 100
  
  GbE, and beyond.
• Experience in PCB design implementations for microprocessors and SoCs (ARM, RISC-V, MPSoC, or equivalent), understanding the physical routing constraints and signal integrity limitations of high pin‑count BGA packages including escape routing, via-in-pad usage, and power delivery network design beneath the device.
• Optimize high-speed connector and backplane interfaces for minimum via stub and maximum channel insertion loss margin.

• Architect and design low‑impedance power delivery networks (PDNs) for high‑current, noise‑sensitive devices including switch ASICs, microprocessors, FPGAs, and DDR memory, with target impedance profiles defined across the full frequency range of interest.
• Perform PDN simulation using frequency‑domain tools to verify decoupling capacitor placement, value selection, and plane resonance suppression.
• Execute power integrity (PI) measurements including VNA‑based PDN impedance measurements, time‑domain load transient validation, and switching…