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Analog IC Layout Engineer Brain-Interface SoC; Equity
Job in
South San Francisco, San Mateo County, California, 94083, USA
Listed on 2026-07-01
Listing for:
Neuralink
Full Time
position Listed on 2026-07-01
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
Neuralink is seeking an Analog IC Layout Engineer in South San Francisco to design state-of-the-art layouts for mixed-signal and analog circuits. The candidate should have over 2 years of experience in IC layout design, especially with FinFET technologies. Responsibilities include reviewing layouts and verifying IC mask layouts. The position offers a competitive salary range of $83,000 - $139,000 and excellent benefits including medical, dental, vision insurance, and equity compensation.
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