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Senior ASIC Verification Engineer — SoC DSP Equity
Job in
South San Francisco, San Mateo County, California, 94083, USA
Listed on 2026-08-22
Listing for:
Neuralink
Full Time
position Listed on 2026-08-22
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Neuralink is seeking ASIC Design Verification Engineers to advance verification of SoC modules for its implant-focused brain-computer interface initiatives. The role emphasizes high-throughput, low-power DSP blocks and robust verification strategies with System Verilog and UVM.
The team conducts architecture and logic implementation, builds test benches, and expands coverage while aligning with Neuralink’s mission to transform medical technology and human-computer interaction.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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