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Low-Power Digital IC Design Engineer Intern
Job in
South San Francisco, San Mateo County, California, 94083, USA
Listed on 2026-09-04
Listing for:
NeuroTechX
Apprenticeship/Internship
position Listed on 2026-09-04
Job specializations:
-
Engineering
Hardware Engineer
Job Description & How to Apply Below
Neuralink seeks experienced engineers for a Digital IC Design Engineer Intern role focused on next-generation chip architectures and hardware accelerators. You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a compact, agile team to push the boundaries of energy efficiency and silicon technology.
The position emphasizes hands-on RTL, micro-architecture, and verification work, with opportunities to influence silicon bring-up and test
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