Digital IC Design Intern -Gen Brain Interfaces
Job in
South San Francisco, San Mateo County, California, 94083, USA
Listed on 2026-09-10
Listing for:
Neuralink
Apprenticeship/Internship
position Listed on 2026-09-10
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Neuralink in California is seeking a Digital IC Design Engineer Intern to contribute to micro-architecture design and RTL implementation of low-power accelerators and SoC components for next-generation brain-computer interfaces.
You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team, tackling energy efficiency, performance, and verification challenges on silicon bring-up.
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