Principal ASIC Package Design Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass‑producing the highest‑power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy‑lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast‑paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply.

We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip‑chip BGA (FC‑BGA) and multi‑chip module (MCM) solutions. This role owns the end‑to‑end package strategy for high‑performance mixed‑signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first‑pass success for complex, high‑speed, power‑dense ASICs.

• Own ASIC package architecture for FC‑BGA and MCM solutions, including substrate stack‑up, ball‑map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package‑level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long‑term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi‑die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC‑BGA packages for high‑pin‑count ASICs with high‑speed Ser Des, dense power grids, and RF signal content.
• Define and review substrate stack‑ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co‑optimize die floor plans and package interfaces.
• Own package‑level SI/PI strategy, including high‑speed digital interfaces (e.g., Ser Des, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy.
• Lead thermal architecture at the package level, including lid selection, TIMs, heat‑spreaders, and mechanical interfaces to system cooling.
• Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
• Drive material selection, substrate technology choices, and assembly process optimization.

• Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC‑BGA.
• Proven experience delivering high‑pin‑count, high‑performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power‑dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high‑speed digital or mixed‑signal SoCs.
• Familiarity with aerospace, space, or high‑reliability electronics.
• Experience defining packaging strategy…