RTL Design Engineer, Cloud TPU

Google place Sunnyvale, CA, USA

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
• Experience in ASIC RTL design using System Verilog or Verilog.
• Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS.
• Experience with SoC bus protocols (e.g., APB, AHB, or AXI) and register-mapped architectures.

• Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture.
• 2 years of experience in ASIC design, specifically designing management and cont rollability subsystems or SoC chassis logic (e.g., Resets, Clocking, Fuse, or Security).
• Experience with physical design teams to resolve congestion or timing issues in high-density control blocks.
• Experience in digital design fundamentals, including state machines, clock domain crossing (CDC), and reset synchronization, low-power design techniques.

Familiarity with SoC bus protocols (e.g., APB, AHB, or AXI) and register-mapped architectures.

• Understanding of sideband protocols (e.g., I2C or SPI) and hardware-software interface (HSI) design.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an RTL Design Engineer for management and cont rollability, you will own the critical logic that governs our next-generation data center accelerators. You will architect and implement the foundational SoC infrastructure, including reset sequences, secure boot, and register maps, that ensure our silicon is manageable, secure, and performant. You will collaborate closely with software, architecture, and physical design teams to deliver control subsystems that power the future of AI hardware at scale.

You will have the opportunity to address technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We re the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Translate high-level management requirements into detailed sub-block specifications and develop high-quality System Verilog for features like secure boot, reset controllers, and…