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Senior ASIC RTL Design Engineer - Memory IP; LPDDR/DDR
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-02-16
Listing for:
Synopsys, Inc.
Full Time
position Listed on 2026-02-16
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading semiconductor company in Sunnyvale seeks an experienced digital design engineer with a strong background in RTL coding and ASIC design. The role requires at least 5 years of experience with a focus on Verilog/System Verilog, along with proficiency in debugging and Synopsys EDA tools. Ideal candidates are analytical, detail-oriented, and effective communicators, eager to advance next-generation memory IP.
This role offers competitive benefits and the opportunity to impact the semiconductor industry significantly.
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Position Requirements
10+ Years
work experience
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