Senior DFT & STA Engineer - Timing Closure ASICs
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-02-16
Listing for:
Google Inc.
Full Time
position Listed on 2026-02-16
Job specializations:
-
Engineering
Systems Engineer, Electrical Engineering, Hardware Engineer
Job Description & How to Apply Below
A leading technology company in Sunnyvale, CA, is seeking a Senior DFT Static Timing Analysis Engineer to shape AI/ML hardware acceleration. This role involves creating and validating test mode timing constraints, performing static timing analysis, and collaborating with teams to optimize design for the next generation of TPU technology. The ideal candidate will have extensive experience in DFT architectures and a strong educational background in Electrical Engineering or related fields.
A competitive salary is offered, along with various benefits.
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Position Requirements
10+ Years
work experience
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