SR HW Signal INTEGRITY Engineer; Ansys HFSS, Cadence Allegro, PCB

SR STAFF Signal Integrity Engineer (Ansys HFSS, Cadence Allegro, PCB, Ser Des)

Fulltime position – 100% Remote from within the USA only

CONFIDENTIAL: Publicly traded computer HARDWARE infrastructure platform solutions company with over $5 Billion in sales whose stock price has grown over 200% in the last year because their products and services are used within Ai Data Centers.

50 Gb/s and higher Signal Integrity design within a PCB stack-up, and off the board (connectors & cables)

The Design Engineering team is experiencing dramatic growth in the USA and has several newly created openings at different levels ranging from SR Engineer, Staff, SR Staff,
Principal
. In general, the Signal Integrity Engineer provides design guideline and support to system architecture design, board layout, product bring up, debug, validation, and factory builds. They will also perform testing, simulation, validation and qualification of systems and makes design adjustments as needed.

The Signal integrity Engineer works in cross-functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high-quality product development.

• Define and develop and validate Signal Integrity for next generation technologies for Networking, Server, and Storage products used in Hardware Platform Solutions for HPC – High Performance Computing and Ai Data Centers
  .
• Models high-density I/O's on PCB
  s,
  packages
  , connectors and probe cards with respect to parameters such as reflections, bandwidth, and crosstalk.
• Lead the design, development and implementation of technical solutions for complex Signal Integrity projects, involving multiple domains. Participate in project planning and scheduling.
• Strong knowledge in simulation tools like Hspice, Sigrity, ADS, Ansys SIwave, HFSS 3D.
• Strong knowledge of Signal Integrity and Power Integrity fundamental concepts.
• Strong experience in Package and PCB modelling is required.
• Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies.
• Should be able to analyze and review the layout files related to Signal Integrity and Power Integrity problems
  .
• Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis.
• Conducting Simulation of memory interfaces for Board and Package
  , and High-Speed Serial IO interfaces for Board and Package.

• Must have BSEE (or similar) and 7+ years of experience with high-speed Signal Integrity design and evaluation. This includes Signal Integrity within a PCB stack up, and off the board (board to board connectors, ribbon cables, coaxial cables). This person should serve as the SME in the planning of digital PCB Stack Up Designs
  , simulation, lab verification, and troubleshooting while working on 50 Gb/s or higher (in support of Ai data centers) with large stacks (15+ layers, preferably 40 layers).
• Should be Signal Integrity SME (Subject Matter Expert) and skilled using Ansys
  HFSS
  , Ser Des Design,
  Cadence Allegro
  , and Sigrity
  , Keysight ADS (Advance Design Systems) for EDA (Electronic Design Automation),
  Ansys SIwave, Siemens Hyperlynx, Matlab, VNA (Vector Network Analyzer).
• Should have expertise in Signal Integrity, SIPI, Ser Des, PCIe, PAM4 – PCB Board & Package – Simulation & Modeling.
• 100% remote but bust live in the USA. Sponsorship is a possibility for the right skillset.
• Must have great English communication skills and ability to work with teams located around the globe. Proven ability to articulate requirements and vision to large and diverse audience through architecture specs and give verbal presentations in technical forums.