Hardware Engineer Sr

- Hardware Engineer

Location:

Sunnyvale, CA (Onsite)
Duration: 12 Months

Minimum 15+ years of experience in Physical Design with advanced node tape-out (3nm/5nm/7nm) experience. Full chip level experience in one of the following is a must:

• Full‑Chip STA with constraints clean‑up, eco generation, driving STA methodology
• Full‑Chip implementation/partitioning, bump planning
• Full‑Chip Physical Verification, cleaning up, LVS expertise
• RTL2
  
  Gate LEC debugging skills, functional eco generation capability is an added advantage

Proficient in TCL/Perl/Python scripting.
Excellent debugging skills.

• Requires in‑depth knowledge and experience
• Solves complex problems; takes a new perspective using existing solutions
• Works independently; receives minimal guidance
• Acts as a resource for colleagues with less experience
• Represents the level at which career may stabilize for many years or even until retirement
• Uses best practices and knowledge of internal or external business issues to improve products/services or processes
• Typically resolves complex problems or problems where precedent may not exist
• Often leads the work of project teams; may formally train junior staff
• Works independently

Bachelor’s degree in Engineering