SoC Quality and Reliability Engineer, Google Cloud
Listed on 2026-02-23
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Engineering
Systems Engineer, Electrical Engineering, Hardware Engineer, Electronics Engineer
SoC Quality and Reliability Engineer, Google Cloud
Google, Sunnyvale, CA, USA
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- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with semiconductor manufacturing, chip design, or device physics.
Experience in silicon or hardware quality, such as reliability testing and product lifecycle standards.
- Experience working with foundry or advanced packaging processes.
- Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in semiconductor reliability and manufacturing processes (fab, assembly, test), or IC and packaging failure mechanisms and related failure analysis.
- Experience in data analytics, especially to identify commonalities and abnormalities.
- Experience in chiplets, and high power devices.
- Familiarity with test methods and hardware for silicon qualification (e.g., High-Temperature Operating Life (HTOL) chambers, Electrostatic Discharge (ESD), Latch-Up (LU), etc.).
- Knowledge of design-for-reliability guidelines and implementation techniques.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Quality and Reliability Engineer for Google Cloud, you will lead the development of design-for-reliability guidelines and drive the adoption of advanced technologies to optimize silicon production and reliability. You will be responsible for ensuring that High Performance Computing (HPC) SOC products meet stringent quality requirements by collaborating across design, manufacturing, and hardware teams to execute comprehensive test plans. Additionally, you will own the cross-functional investigation and root-cause analysis of integrated circuit (IC) issues to develop effective solutions in a production environment.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities- Own the development of design-for-reliability guidelines, collaborating with subject area experts (e.g., DFBI, SER, EMIR, PERC, HVDRC, Margining, etc.).
- Define and execute silicon and package qualification…
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