ASIC Manager

This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office.

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next.

We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

Role focuses on advanced silicon, block and system‑level verification. Responsibilities include designing, developing, analyzing, troubleshooting, and debugging complex ASIC and SoC verification environments, system models, and methodologies. Supports development of products, services, and solutions within HPE’s networking portfolio. Requires strong expertise in hardware verification engineering disciplines, methodologies, and tools—including System Verilog, UVM, System

C modeling, and hardware emulation platforms.

Leads and mentors a team of verification engineers responsible for executing ASIC/SoC verification plans, developing testbench infrastructure, and ensuring high‑quality functional and system‑level validation. Partners closely with architects, RTL designers, and cross‑functional teams to align verification execution with product architecture and program goals.

Applies advanced subject matter knowledge to manage staff activities in solving common and complex business/technical issues within established policies. Manages exempt individual contributors and/or supervisors. Has accountability for results of a major program in terms of cost, direction and people management. Provides guidance on process improvements and recommends changes in alignment with business tactics and strategy for area of responsibility. Plans, manages and monitors operational/tactical activities of Staff.

Staff members' work may involve strategic issues. Recruits and supports development of direct staff members. Typically reports to MG2 or Director.

• Leads a team of verification engineers focused on ASIC/SoC verification using System Verilog, UVM, System
  
  C modeling, and emulation platforms
• Drives development and deployment of scalable, reusable verification architecture, methodologies, and infrastructure
• Creates verification plans, schedules, milestones, and priorities based on product architecture and program needs
• Ensures high‑quality verification coverage, including functional, power, performance, and system‑level validation
• Supports System
  
  C/TLM modeling strategy to enable early firmware development and alignment with RTL verification
• Oversees emulation and acceleration workflows to improve verification throughput and software validation readiness
• Manages team execution, schedules, deliverables, and continuous improvement in efficiency, automation, and coverage closure
• Collaborates with architects, RTL design leads, program management, validation, and system engineering to communicate status and drive issue resolution
• Works with EDA vendors, emulation platform providers, and global development partners to support tool and flow needs
• Identifies opportunities for methodology improvements, flow innovation, and productivity enhancements
• Provides people leadership including hiring, mentoring, performance planning, and skill development

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent; advanced degree preferred
• Typically 7-10 years of ASIC/SoC design and verification experience
• 2–5+ years of people management or technical leadership in verification or silicon development
• Strong hands‑on expertise in System Verilog, UVM methodology, and System
  
  C/TLM modeling
• Experience with…