ASIC Power Analysis Engineer

Position: Silicon CAD Engineer IV

Type: Full-time position

Compensation: $50-$70 per hour

Location: Sunnyvale, CA, USA

Commitment: 10–40 hours/week

• Perform comprehensive power analysis at various design stages, spanning from RTL to GDSII
• Contribute to the development, improvement, and automation of power analysis flows
• Gather and analyze large datasets for power modeling via automated processes
• Investigate and address power inefficiencies and provide actionable feedback to the RTL design team

• Demonstrated experience with RTL-to-GDSII design flow usage and development in advanced technology nodes (7nm and below)
• Expertise in low-power implementation and signoff, including power gating, multiple voltage rails, and Unified Power Format (UPF) usage
• Proven experience in power analysis and reduction utilizing industry-standard tools such as Prime Time PX and Prime Power
• Proficiency in scripting languages, with a strong emphasis on Python and ML/AI frameworks
• Working knowledge of RTL design principles
• Experience in RTL power optimization using tools such as Power-Artist
• Ability to learn quickly, explore new ideas, and iterate rapidly to achieve optimal results
• Experience with synthesis and Place and Route (PnR) flows
• Experience analyzing Intellectual Property (IP) design for power characteristics and building run-time estimation models for software or firmware teams
• Skills in data analysis and data modeling, including application of machine learning approaches
• Bachelor’s degree in Electrical/Computer Engineering or Computer Science required
• Master’s degree preferred but not required

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