Director of Engineering

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large‑scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Cerebras' current customers include top model labs, global enterprises, and cutting‑edge AI‑native startups. OpenAI recently announced a multi‑year partnership with Cerebras to deploy 750 megawatts of scale, transforming key workloads with ultra high‑speed inference.

Thanks to the groundbreaking wafer‑scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU‑based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real‑time iteration and increasing intelligence via additional agentic computation.

Cerebras Systems Inc. has multiple openings for Director of Engineering.

Title:

Director of Engineering

• Own the end‑to‑end verification roadmap for a next‑gen wafer scale engine, establishing the formal, block/SOC UVM and gate‑level simulation methodologies and ensuring successful project delivery.
• Sign off on the design verification of next‑generation AI/ML accelerators by analyzing functional and code coverage, gate‑level simulation results, regression trends, and reported bugs, leveraging AI/ML hardware verification expertise.
• Oversee verification and validation of complex architecture and design by defining test plans, testing methodologies and strategies in coordination with architecture, RTL, firmware, compiler, kernel and emulation teams.
• Direct, review, and approve design modifications and technical changes in engineering projects.
• Direct engineering staff in the preparation and evaluation of verification test cases using Verilog & System Verilog hardware description languages, ensuring that testing processes meet project standards and technical requirements.
• Confer with executive management to discuss project specifications and timelines for next‑gen products.
• Provide updates on goals for monthly program reviews by using tools like Microsoft PowerPoint, Excel and Word documentation.
• Develop standards and procedures for design verification work. Define roadmap, methodology and tools for performing design verification.
• Advocate and direct implementation of scripts and tools to automate process using scripting languages like Python or Perl.
• Establish technical goals within broad outlines provided by top management.
• Monitor progress against goals and report to executive management on progress against those goals using project tracking tools such as Confluence, Excel and Microsoft Project.
• Perform administrative functions, such as reviewing or writing reports, managing and approving contracts and expenditures, enforcing rules, or purchasing of materials or services.
• Give feedback to employees on their performance. Advise executive management on salary increase and stock awards.
• Direct recruitment, placement, and evaluation of engineering project staff.

Master’s degree or foreign equivalent degree in Electrical and Electronic Engineering, Computer Engineering, or a related field and 5 years of experience as Engineering Manager, Design Verification Engineer, Director of Engineering, or a related occupation required.

The required work experience must include 5 years of experience using the following skills:

• Scripting language:
  Python;
• Verilog & System Verilog hardware description languages;
• UVM verification methodologies;
• Gate level simulations of hardware;
• Validation of AI/ML accelerator architecture features using Zebu emulator;
• Ability to sign off verification of AI/ML accelerator hardware by reviewing regression results, bug reports, and coverage metrics; and
• Ability to manage and coordinate design verification activities across software, RTL design, architecture,…