Senior TPU RTL Design Engineer Speed Interconnects
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2026-03-08
Listing for:
Google
Full Time
position Listed on 2026-03-08
Job specializations:
-
Engineering
Systems Engineer, Engineering Design & Technologists -
IT/Tech
Systems Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A leading technology firm in Sunnyvale is seeking an experienced ASIC Design Engineer to lead cutting-edge TPU hardware development. The role demands expertise in ASIC design, collaboration across teams, and leadership of the RTL lifecycle. Candidates should possess a Bachelor's degree and 5 years of relevant experience. This position offers a competitive salary range of $156,000-$229,000, along with bonuses and equity.
Join a dynamic team committed to innovation in AI and machine learning.
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Position Requirements
10+ Years
work experience
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