Senior ECAD Library Engineer, Platforms Infrastructure

Senior ECAD Library Engineer, Platforms Infrastructure

Location:

Sunnyvale, CA, USA

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related technical field, or equivalent practical experience.
• 4 years of experience developing libraries for Cadence schematic and PCB design software (e.g., Concept HDL, Allegro).
• Experience with STEP file integration into the library.
• Experience developing symbols and footprints for BGA packages, high‑density connectors, and alternate symbols and footprints.
• Experience working within IPC standards for padstacks, footprints, and naming conventions.
• Experience with DFx principles for PCB manufacturing, assembly, and test.

• Experience with PCB Layout.
• Experience with Allegro SKILL, Python, and Windows command line programming.
• Experience with Git for revision control.

As an ECAD Librarian you will manage the Digital Network Architecture (DNA) of our hardware, building and organizing libraries that enable engineers to design the world’s most powerful computing infrastructure. From large Ball Grid Array (BGA) packages to interconnects, you will ensure that every component is built for precision, manufacturability, and global scale.

In this role, you will bridge the gap between Electrical Engineering, printed circuit board layout, and manufacturing. You will architect a library system that supports seamless routing and hardware life cycles, ensuring Google’s custom‑built servers move from concept to high‑volume manufacturing, directly impacting the infrastructure that powers services for millions of users.

Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google’s services, enabling complex and unique computational challenges with cutting‑edge custom hardware designed and made in‑house.

US base salary range for this full‑time position is $159,000‑$231,000 plus bonus, equity, and benefits. Compensation details are determined by role and location; additional information will be provided during hiring.

• Manage the library, build footprints and symbols, organize Part Table File (PTF) tables, and continually improve the library set‑up and structure.
• Support electrical engineering and PCB layout based on the library perspective, such as pin/part arrangement for schematic drawing, reasonable routing, and package keep‑out.
• Work with manufacturing and component engineers to create common footprints for non‑identical parts.

Google is an equal opportunity and affirmative action employer. We are committed to building a workforce that reflects the users we serve. All employment decisions are made without regard to race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition. For more information, see Google’s EEO Policy, Belonging at Google, and How we hire.