Design Verification Engineer

DESIGN VERIFICATION ENGINEER

City:
Sunnyvale

State/Province:
California

Posting

Start Date:

5/28/26

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients' most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world.

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Job Description:

Job Description

Job Description:

Design verification engineer:

PREFERRED EXPERIENCE:

* Architected and developed complex verification environments in System Verilog, including scripting using Perl, Ruby, Make, or the likes.

* Exposure to RTL design, software development, formal verification, or other related domains.

* Good understanding of computer organization/architecture.

* Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics

KEY RESPONSIBLITIES:

* Write tests, sequences, and testbench components in System Verilog and UVM along with formal to achieve verification of the design.

* Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.

* Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.

* Collaborate with architects, hardware engineers, and multiple IP development groups.

* Drive formal verification for the block and write formal properties and assertions to verify the design

* Responsible for verification quality metrics like pass rates, code coverage and functional coverage

ACADEMIC CREDENTIALS:

* Bachelors or Masters degree in computer engineering/Electrical Engineering preferred

Mandatory

Skills:

System Verilog,Verification and Validation .

Experience:

5-8 Years .

The expected compensation for this role ranges from $60,000 to $148,500 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we.

Join a business powered by purpose and a place that empowers you to design your own reinvention.