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ASIC Design Verification Engineer, Cloud

Job in Sunnyvale, Santa Clara County, California, 94086, USA
Listing for: Google
Full Time position
Listed on 2026-06-03
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 117000 - 166000 USD Yearly USD 117000.00 166000.00 YEAR
Job Description & How to Apply Below
ASIC Design Verification Engineer, Google Cloud

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

** Early*
* Experience completing work as directed, and collaborating with teammates; developing knowledge of relevant concepts and processes.

*
* Minimum qualifications:

*
* + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

+ 1 year of experience in design verification.

+

Experience with System Verilog/Verilog.

*
* Preferred qualifications:

*
* + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

+

Experience with Universal Verification Methodology (UVM) test benches and methodologies.

+ Experience developing and executing test plans.

+ Familiarity with coverage analysis tools (e.g., Verdi, Questa).

+ Proficiency in System Verilog, including object-oriented programming, System Verilog Assertions (SVAs) and functional coverage.

+ Excellent problem-solving and debugging skills.

** About the job*
* In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $117,000-$166,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google () .

** Responsibilities*
* + Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.

+ Create a constrained-random verification environment using System Verilog and Universal Verification Methodology (UVM).

+ Identify and write all types of coverage measures for stimulus and corner-cases.

+ Debug tests with design engineers to deliver correct design blocks.

+ Close coverage measures to identify verification holes and to show progress towards tape-out.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google's EEO Policy ()…
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