ASIC Design Verification Engineer, TPU Compute

Location: Sunnyvale, CA, USA

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience in verifying digital logic at RTL using System Verilog/UVM for ASICs.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
• Experience with three or more SoC projects/cycles.
• Experience verifying compute IPs.
• Strong problem‑solving, analytical, and communication skills, with the ability to work effectively in a team environment.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an ASIC Design Verification Engineer, you will be part of a team developing cutting‑edge ASICs used to accelerate computation in data centers. You will have dynamic, multi‑faceted responsibilities in areas such as project definition, design verification and silicon bring‑up. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create a constrained‑random verification environment using System Verilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner‑cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape‑out.

The US base salary range for this full‑time position is $138,000‑$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

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See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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