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RTL Design Engineer, TPU Integration and Automation

Job in Sunnyvale, Santa Clara County, California, 94086, USA
Listing for: Google
Full Time position
Listed on 2026-06-05
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 138000 - 198000 USD Yearly USD 138000.00 198000.00 YEAR
Job Description & How to Apply Below
RTL Design Engineer, TPU Integration and Automation

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

** Mid*
* Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

*
* Minimum qualifications:

*
* + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

+ 4 years of experience in ASIC design, design automation, or a related field.

+ Experience programming in Python and shell scripting, and experience with System Verilog or other hardware description languages.

+

Experience with EDA tools and typical ASIC design and verification flows.

+

Experience with version control systems (e.g., Git, Perforce) and with build systems (e.g., Bazel, Make).

+

Experience with continuous integration systems (e.g., Jenkins).

*
* Preferred qualifications:

*
* + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

+

Experience with data visualization tools and dashboard creation.

+ Understanding of digital design principles.

+ Proven ability to work independently on end-to-end tasks and projects.

+ Strong communication and collaboration skills, with the ability to work effectively in a team environment.

+ Excellent problem-solving and debugging skills.

** About the job*
* In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google () .

** Responsibilities*
* + Own Compute IP releases to the SoC. Enhance scripts and flows for SoC releases to reduce manual effort and cycle time for IP releases.

+ Use Python to improve efficiency and quality in top-level IP assembly, focusing on connectivity and configuration.

+ Automate IP versioning and integration for cross-project consistency.

+ Liaise between Design and Physical Design teams to refine automation for reliable, high-quality branch handoffs. Partner with multi-functional teams to deploy automation for development pain points and document methodologies

+ Maintain automated systems to validate tool flows and design health.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google's EEO Policy () ,Know…
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