Verification Engineer, Digital Signal Processing

Verification Engineer, Digital Signal Processing

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

** Mid*
* Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

*
* Minimum qualifications:

*
* + Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.

+ 8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.

+

Experience with scripting in Python, Perl, or Makefile for automation.

*
* Preferred qualifications:

*
* + Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.

+

Experience with Mixed-Signal verification techniques such as Real Number Modeling (RNM, System Verilog-Wreal) or System Verilog-AMS.

+ Functional knowledge of adaptive equalization architectures (FFE/DFE) and timing recovery loops.

+ Programming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.

** About the job*
* In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google () .

** Responsibilities*
* + Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or System

C) using bit-exact and fixed-point verification methodologies.

+ Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.

+ Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or System Verilog-AMS.

+ Design, implement, and maintain scalable UVM-based simulation environments, System Verilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be,…