Senior ASIC Design Engineer, Cloud

Senior ASIC Design Engineer, Google Cloud

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

** Mid*
* Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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* Minimum qualifications:

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* + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

+ 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or System Verilog.

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* Preferred qualifications:

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* + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

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Experience with three or more SoC projects/cycles.

+ Familiarity with the full ASIC flow (DFT, synthesis, PnR), Ser Des behavior, and scripting (Python, Tcl, or Perl) to drive technical execution.

+ Expert knowledge of NoC/Memory architecture, flow control, and performance tuning.

+ Proven ability to lead cross-functional efforts with software and system hardware teams, from initial library RTL development through to silicon bring-up.

+ Advanced RTL design skills with mastery of multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.

** About the job*
* In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Design Engineer, you will architect and implement SoC-level RTL for our next-generation data center accelerators. You will design high-performance subsystems, build the foundational SoC infrastructure, including clocking, reset, error handling, and chip management that powers our silicon. In this highly cross-functional role, you will be offered a "big picture" view of the product life-cycle from concept to production, requiring close collaboration with software and hardware teams to deliver accelerators.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google () .

** Responsibilities*
* + Drive the complete RTL life-cycle from initial microarchitecture, coding, and documentation to sign-off readiness (Lint, CDC, synthesis) for high-performance designs meeting strict PPA targets and quality guidelines.

+ Collaborate with system architects to align on chip-level bandwidth, latency, and power objectives, and partner with the Verification and Physical Design teams to define test plans and achieve timing closure.

+ Identify test requirements, define methodology/tools, and execute testing of silicon systems; drive protocol resolution and lead post-silicon bring-up to validate link integrity and subsystem performance.

+ Influence designs to enhance testing, validation, and debugging capabilities, while establishing third-party IP requirements and driving the selection process.

+ Develop and maintain policies, processes, procedures, methods, and documentation for silicon deliverables to enhance efficiency, productivity, and project sustainability.

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