R&D Engineering, Sr Architect

# R&D Engineering, Sr Architect Sunnyvale, California, United States Apply
* Overview* Job Description
* Benefits* How We Hire## Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

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Job Description
** Date posted
** 05/31/2026###
** Category
* * Engineering
** Hire Type
** Employee
** Job
** 17656
** Base Salary Range** $226000-$338000
** Remote Eligible
** No
** Date Posted
** 05/31/2026

We Are     Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are     You have spent years building EDA software that has to hold up under real-world custom IC design pressure, the kind where a layout decision at 3nm can make or break a tape-out schedule. You know that the difference between a tool designers trust and one they route around is usually in the details, the algorithm that shaves two hours off a placement run, the infrastructure decision that makes GAA process nodes actually usable instead of theoretically possible.
You think in systems, not just features. When someone asks for a new routing capability, you are already mapping the impact on existing flows, the training burden on designers, and the maintenance cost three releases from now. You have used Custom Compiler or Virtuoso enough to know where the pain points live, and you care about solving them at the architecture level, not patching them at the UI level.
You are comfortable setting direction for junior engineers while still writing code yourself. You do not need a perfect spec to get started. You talk to IP teams, understand what 2nm and 14A nodes actually demand, and build tools that make their jobs easier. At Synopsys, you will work on the platform that powers custom IC design across the industry, and what you architect will ship to customers building the next generation of chips.
What You'll Be Doing     Architect and develop placement and routing infrastructure for Custom Compiler targeting advanced GAA and FinFET process nodes including 5nm, 3nm, 2nm, and 14A     Design and implement layout automation features that directly improve designer productivity in circuit layout for cutting-edge process technologies     Set technical direction and operational specifications for Custom Compiler software based on analysis of customer workflows and EDA ecosystem requirements     Drive research and development of new algorithms and tools that address real bottlenecks in custom IC layout for advanced nodes     Collaborate with Synopsys IP teams to integrate and proliferate Custom Compiler layout automation technologies across internal design flows     Mentor and guide junior engineers on software architecture, coding standards, and quality practices specific to EDA tool development     Manage maintenance and evolution of existing tool sets and infrastructure across product releases, balancing new feature development with stability     The Impact You Will Have     Enable designers to complete complex custom IC layouts for 3nm and below process nodes faster and with fewer iterations     Reduce time-to-tapeout for Synopsys IP teams and external customers through smarter placement and routing automation     Shape the technical roadmap for Custom Compiler, influencing how thousands of analog and custom designers work daily     Accelerate adoption of advanced GAA and FinFET technologies by making them accessible through better EDA tooling     Build…