Senior R&D Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent time deep in the physics of how signals move through silicon, and you know that the difference between a chip that works at speed and one that doesn't often come down to parasitic effects most people never see. Maxwell's equations are not abstract theory to you; they are the foundation of how you think about interconnect behavior at 3nm and below.

You are comfortable moving between electromagnetic theory and production C++ code. You can derive a quasi-static model in the morning and spend the afternoon optimizing a data structure that must handle billions of elements without falling over. When a foundry sends you a challenging new process corner or a customer describes a signoff failure in a CPU design, you do not panic, you dig in, reproduce it, and figure out what the model is missing.

Building things that must be right matters to you. Not approximately right for a demo, correct when someone tapes out a chip worth millions of dollars. You ask hard questions about accuracy versus runtime tradeoffs, and you care about both. You know that an extraction model that adds 10% runtime but catches a critical coupling issue is worth it, and you can articulate why to both engineers and product managers.

At Synopsys, you will work on StarRC, the tool that sets the standard for parasitic extraction across the industry, and what you build will directly affect whether advanced designs close on schedule.

• Research, design, and implement new transistor level extraction capabilities for StarRC, focusing on modeling accuracy for FinFET and gate-all-around devices at 3nm, 2nm, and beyond
• Develop parasitic models for interconnect capacitance, inductance, and resistance using pattern-matching techniques and field solver methods
• Apply computational electromagnetics principles to solve complex extraction problems for advanced process nodes
• Design efficient algorithms and data structures in C++ that handle massive layout datasets while maintaining extraction accuracy and runtime performance
• Collaborate with engineers across layout, simulation, timing, and physical verification teams to ensure StarRC integrates seamlessly into customer signoff flows
• Work directly with foundries and customers to resolve extraction challenges in CPU designs, 3D IC systems, and advanced packaging structures

• Enable accurate signoff for chips at the most advanced process nodes, directly affecting whether billion-dollar designs can tape out on schedule
• Improve extraction runtime and capacity so customers can close timing on larger, more complex SoCs without sacrificing accuracy
• Delivering capabilities that help foundries and design teams understand parasitic effects in new process technologies before they become yield problems
• Strengthening StarRC's position as the gold standard extraction tool by solving problems competitors cannot
• Help customers across CPU, AI accelerator, and memory design teams achieve first-pass silicon success by catching parasitic issues early
• Shape the technical direction of extraction technology through direct collaboration with leading foundries and design houses

• MS or PhD in Electrical Engineering, Computer Science, or Computer Engineering with 1+ years of relevant EDA or CAD software development experience
• Strong background in computational electromagnetics, including experience with full-wave or quasi-static EM modeling, Maxwell's equations, and numerical methods such as FEM, BEM, or MoM
• Hands-on experience with transistor level parasitic extraction or modeling
• Proficiency in C++ programming, algorithm design, and data structures for performance-critical software systems
• Understanding how parasitic effects impact circuit…