R&D Engineering, Architect

You Are

You are a highly motivated Engineer with over 15+ years of hands‑on experience in synthesis, place and route (P&R) and sign‑off. You have a robust understanding of the most advanced Interface IP Protocol designs and are eager to work closely with R&D on driving product improvement and developing advanced CAD reference flow. Your technical expertise allows you to demonstrate differentiated PPA results on Synopsys IP portfolio.

You thrive in dynamic environments and possess excellent communication skills. Your background in EE/CS, coupled with your experience with EDA tools like DC, ICC2, Fusion Compiler, PT, ICV and Red Hawk makes you an ideal fit for this role.

• Collaborating with R&D teams to develop leading edge CAD flows for Synopsys IP.
• Demonstrating differentiated PPA results on industry standard Synopsys Interface IP protocol designs.
• Providing technical support to IP developers, key customers and test‑chip tapeouts in leading edge nodes.
• Deliver scalable CAD flows for multiple Synopsys IP to ensure the highest quality and performance of designs.
• Utilizing scripting languages such as Perl and Tcl for automation and optimization tasks.
• Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve processes.

• 15+ years of proven experience in ASIC physical design or CAD flows with expertise in complex SoC at advanced process nodes.
• Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR‑drop/EM analysis, LVS/DRC, and related methodologies.
• Demonstrated experience developing cutting‑edge flows and managing cross‑functional projects in high‑pressure environments.
• Proficiency with state‑of‑the‑art CAD tools such as DC, PT, ICC2/FC, ICV, Red Hawk, and advanced technologies like 5nm, 3nm, 2nm.
• Strong communication, problem‑solving, and project management skills.

• Delivering cutting‑edge CAD flows that are scalable and easily adoptable by designers.
• Accelerating project timelines and reducing time‑to‑market for key IP solutions through expert technical leadership.
• Enhancing CAD flows delivering robust, scalable, and innovative silicon solutions in a fast‑evolving industry.
• Enhancing the performance and efficiency of Synopsys IP design implementation flows.
• Providing critical support that helps key customers overcome their PPA challenges.
• Contributing to the development of new features that keep Synopsys solution at the forefront of the industry.
• Improving the overall quality and reliability of our products through meticulous design and optimization.
• Fostering strong relationships with IP designers, Field AE organization and Tool R&D developers.

• Innovative and detail‑oriented, with a relentless drive for technical excellence.
• Exceptional communicator, adept at collaborating across global teams and with external customers.
• Strong problem‑solver who thrives in challenging, fast‑paced environments.
• Team player who actively contributes to a collaborative and inclusive culture.
• Natural leader and mentor, inspiring others to achieve their best.
• Proactive and adaptable, always seeking opportunities to learn and improve.

Join a world‑class R&D organization at the forefront of IP subsystem innovation. Our multidisciplinary teams work across engineering, EDA tools, product management, and customer success to deliver solutions that power tomorrow’s intelligent systems. We value creativity, technical rigor, and excellence, providing an environment where every member can contribute and grow.