Physical Design Engineer II; Silicon Engineering

Physical Design Engineer II (Silicon Engineering)

Sunnyvale, CA

Space

X is actively developing technologies to enable human life on Mars. We are leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation, providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system — thousands of satellites, consumer receivers, and the software that brings it all together.

This role focuses on developing cutting‑edge ASICs for space and ground infrastructures, expanding Starlink’s performance and capabilities.

• Perform partition synthesis and physical implementation steps (e.g., synthesis, floor planning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency, and other signoff checks).
• Develop and improve physical design methodologies and automation scripts for various implementation steps.
• Collaborate closely with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
• Resolve design, timing, congestion, and flow issues, identify potential solutions, and drive execution.
• Run, debug, and fix signoff closure issues in static timing analysis, noise, logic equivalency, physical verification, electromigration, and voltage drop.

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 3+ years of professional experience working on RTL‑to‑GDSII physical design and/or physical design flow development.

• Experience with industry‑standard EDA tools and understanding of their capabilities and underlying algorithms.
• Knowledge of deep sub‑micron FinFET and CMOS solid‑state physics.
• Understanding of CMOS digital design principles, standard cells, and libraries.
• Understanding of CMOS power dissipation in deep sub‑micron processes (leakage/dynamic).
• Familiarity with CMOS analog circuit and physical design.
• Basic knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows.
• Self‑driven individual with a can‑do attitude, willingness to learn, and the ability to work in a dynamic group environment.

• Ability to work extended hours and weekends as needed to meet critical project milestones.

Pay range:
Physical Design Engineer/Level II: $155,000 – $185,000 per year. Base salary is determined based on job‑related knowledge, skills, education, and experience.

In addition to base salary, you may be eligible for long‑term incentives in the form of company stock, stock options, or long‑term cash awards, discretionary bonuses, and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. Benefits include comprehensive medical, vision, and dental coverage; a 401(k) retirement plan; short‑ and long‑term disability insurance; life insurance;

paid parental leave; discounts and perks; 3 weeks of paid vacation; 10 or more paid holidays per year; and sick leave (5 days for exempt employees).

To conform to U.S. Government export regulations, applicants must be:

• U.S. citizen or national.
• U.S. lawful permanent resident (green card holder).
• Refugee under 8 U.S.C. § 1157.
• Asylee under 8 U.S.C. § 1158, or eligible to obtain the required authorizations from the U.S. Department of State.

Space

X is an Equal Opportunity Employer; employment with Space

X is governed on the basis of merit, competence, and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability, or any other legally protected status.