RTL Design and Integration Engineer

RTL Design and Integration Engineer

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

** Early*
* Experience completing work as directed, and collaborating with teammates; developing knowledge of relevant concepts and processes.

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* Minimum qualifications:

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* + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

+ 1 year of experience in RTL design.

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Experience with digital design and microarchitecture design.

+ Cross-functional experience with DV and PD teams.

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* Preferred qualifications:

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* + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

+ 4 years of RTL design experience.

+ 4 years of RTL design experience and architecting RTL solutions.

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Experience with Linting, CDC, RDC, LEC.

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Experience with Scripting languages (i.e. Python or Perl).

+ Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows.

** About the job*
* In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware.

You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows.

As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $116000 - $166000 (USD) + 15% bonus target + bonus + equity + benefits

Learn more about benefits at Google () .

** Responsibilities*
* + Define and document the microarchitecture for digital designs within the TPU.

+ Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in System Verilog.

+ Collaborate with partner teams to support integration efforts and Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness. Support post-silicon validation and debug efforts.

+ Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.

+ Contribute to the development and enhancement of design tools, flows, and methodologies.

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