TPU RTL Design Engineer, Cloud

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience with RTL Design.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.
• Experience optimizing designs for performance, power, or area.
• Experience collaborating cross-functionally with DV teams on test plan creation and execution.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with CDC, RDC, RTL Linting and LEC.
• Experience with scripting languages (i.e. Tcl, Python or Perl).
• Experience architecting RTL solutions.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. You will be responsible for the microarchitecture, design, and implementation of key digital logic blocks within the TPU.

Your role requires collaborating with cross‑functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver hardware. You will own critical design deliverables and contribute to the continuous improvement of our design methodologies and flows.

US: $138000 - $198000 (USD) + 15% bonus target + bonus + equity + benefits

• Define and document the microarchitecture for digital designs within the TPU.
• Develop high‑quality, performant, and power‑efficient Register Transfer Level (RTL) code, primarily in System Verilog.
• Collaborate with the verification team to develop test plans, debug RTL, and ensure functional correctness.
• Coordinate with the physical design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law.

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