SoC DFT Engineer, Cloud

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring‑up, debug, or validation of DFT features.
• Experience with industry‑standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience with various fault models (Stuck‑at, Transition, Cell‑Aware, Path Delay, etc.).
• Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Experience with industry‑leading EDA tools for DFT, such as Synopsys (Design Compiler, DFT Max) or Siemens EDA (Tessent, Test Kompress).
• Knowledge of test standards (IEEE 1149.1, 1687) and test data formats (BSDL, STIL).

In this role, you will shape the future of AI/ML hardware acceleration. You will drive cutting‑edge TPU technology that powers Google's most demanding AI/ML applications and contribute to custom silicon solutions that support millions of users worldwide. Your expertise will focus on verifying complex digital designs for TPU architecture and integration within AI/ML‑driven systems.

As a DFT Engineer you will define, implement, and deploy advanced Design‑for‑Test (DFT) methodologies—including scan, MBIST, JTAG, and iJTAG—for highly digital or mixed‑signal chips or IPs. You will create silicon test strategies, DFT/DFD architecture, and specifications for next‑generation SoCs, diagnose memory and logic failures with the Silicon Engineering team, and enhance yield, quality, and test cost.

Our AI and Infrastructure team redefines what’s possible by delivering AI and infrastructure at unparalleled scale, efficiency, reliability, and velocity to Google Cloud customers, Googlers, and billions of users worldwide.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $163,000 – $237,000 (USD) + 15% bonus target + bonus + equity + benefits.

• Develop and document DFT strategy, architecture, and test sequences, including hierarchical DFT, memory built‑in self‑test (MBIST), automatic test pattern generation (ATPG), and instrument/joint test action group (I/JTAG), and associated boot‑up and execution sequences.
• Complete all test design rule checks (TDRC) and design changes to fix TDRC violations to achieve high test quality.
• Develop diagnostic databases, software, and hardware for logic and memory fail debug.
• Design and implement system‑level test strategy.
• Implement core DFT circuitry, including insertion and hook‑up of scan chains, DFT compression, logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law.

If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.