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Silicon Photonics Packaging Engineer Co-op

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: NOKIA
Full Time position
Listed on 2026-06-17
Job specializations:
  • Engineering
    Manufacturing Engineer, Packaging Engineer, Electrical Engineering, Mechanical Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Position Details

Number of Positions: 2

Duration: 4 months

Date: Sept 2026 - Dec 2026

Location: Onsite in Sunnyvale, CA, or New York, NY

Education Recommendations

Current M.S. or Ph.D. student in electrical engineering, physics, applied physics, or other similar fields with an accredited university in the USA.

Responsibilities
  • Develop semiconductor and optical packaging processes in-house, or in close partnership with contract manufacturers.
  • Design optical transceiver packages in collaboration with cross-functional teams and stakeholders to ensure package requirements are met.
  • Own Design Rules documents and ensure Design for Manufacturing specifications are met.
  • Perform mechanical integrity and thermal simulations, tolerance analyses and characterization.
  • Drive package debug activities during product validation and qualification.
  • Plan and Drive prototype assembly builds to enable deliveries for early design validation.
  • Apply in-depth knowledge of advanced packaging principles and stay current with new technological advancements.
Qualifications
  • Experience with package and process design/development from design to production.
  • Knowledge of design for manufacturing, 2.5D/3D packaging, and TSVs.
  • Experience with documentation of fabrication, inspection, and assembly processes.
  • Solid interpersonal, communication and problem-solving skills in order to interact with engineering staff, external vendors and contractors effectively.
Nice to Have
  • Understanding of optical epoxies, non-hermetic packaging, and high-volume packaging and thermal analysis of 2.5/3D packages.
  • Experience in the semiconductor chip and wafer-level back-end processing, assembly, and/or packaging.
  • Experience in high-speed electronics package design and/or laser package design.
  • Experience with thermo-mechanical simulations using ANSYS or similar software.
  • Experience with metrology techniques such as SEM/XSEM, confocal microscopy, or acoustic imaging.
  • Familiarity with design and simulations of optical packaging using free space optics or fiber coupling.
EEO Statement

We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.

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