Chip Signal and Power Integrity Engineer

Chip Package Signal and Power Integrity Engineer

Google Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with SI/PI design for chip/package or system PCB.
• Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).

• Master’s degree or PhD in Electrical Engineering or SI/PI.
• Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.
• Knowledge of next-generation memory and chiplet standards, including timing budget, design & sign-off methodologies.
• Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
• Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.
• Proficient in Python, Matlab, or C++ to establish automation flows and advanced data processing/analysis.

As a Chip Package Signal Integrity/Power Integrity (SI/PI) Engineer in the chip implementation team, you will be responsible for the chip package design with signal/power integrity simulation and characterization at the package and system level. You will work with cross‑functional teams including chip design, board design, system design, and vendors, driving chip packaging signal and power implementations to meet electrical requirements.

• Drive chip‑package‑system co‑design by performing SI/PI analysis and optimization to involve in product definition and optimize chip floorplan, power tree structure, net lists, etc. for HPC based on 2.5D/3D package technology.
• Develop Power integrity methodology for advanced package technology and enhance accuracy and productivity.
• Evaluate new package technology development and high‑speed interface IP.
• Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design targets, define boundaries of chip design and explore SI/PI and DFM trade‑offs for package design closure for production.
• Provide feedback on chip floorplan considering package/system routability and SI/PI.

US: $192,000 - $279,000 (USD) + 20% bonus target + equity + benefits.

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