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Physical Design Engineer; Sunnyvale, CA

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Tachyum
Full Time position
Listed on 2026-07-24
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 300000 USD Yearly USD 150000.00 300000.00 YEAR
Job Description & How to Apply Below
Position: Physical Design Engineer (Sunnyvale, CA)

Physical Design Engineer

Location:

Sunnyvale, CA

Responsibilities
  • Responsible for implementation of ultra‑high performance and low‑power data processing chip
  • Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs
  • Floor‑planning, experimenting with placement and routing techniques for better PPA
  • Do timing closure for very high frequency designs with possible hand placement of logic when needed
  • Help define low‑latency/low‑skew clock tree methodology/design
  • Help define appropriate power grid structures to meet EM/IR goals
  • Scripting and automating flows to improve turn‑around times
Qualifications
  • Member of core team responsible for the crafting and timely delivery of PD partitions
  • Strong communication and interpersonal skills required to work with our global design team
  • Successful track record of mentoring junior engineers and interns (plus)
  • More than 5 years of experience in high‑performance semiconductor designs
  • Verilog knowledge and an understanding of ASIC design flow
  • Expertise in logic synthesis, prototyping, timing analysis, floor‑planning
  • Expertise in flow automation (Perl, Tcl, Python) and understanding of full PD methodology
  • Experience with Innovus on 7nm or lower technology nodes
  • A background in computer architecture is desirable
  • Ability to learn new technologies and apply that knowledge quickly
  • Proven track record demonstrating the ability to meet project milestones and deadlines
  • BS or MS Degree in Electrical Engineering or Computer Science
  • Familiarity with basic synthesizable RTL designs (flops, FIFOs, clock domain crossing) is a plus
  • Strong familiarity with PCIe, Ethernet (100G and above), DDR4
  • Ability to create regression scripts to run individual and batch jobs on grid
Benefits
  • Competitive salary and benefits package
  • Opportunities for professional development and advancement
  • International environment and further career progression
  • Getting in touch with bleeding edge technology
  • Collaborative and supportive work environment

Compensation:
Base salary $150,000 to $300,000 plus equity and benefits.

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