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Senior Design Verification Engineer – Emulation Expert

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Hobbsnews
Full Time position
Listed on 2026-07-26
Job specializations:
  • Engineering
    Test Engineer, Quality Engineering
Salary/Wage Range or Industry Benchmark: 153500 - 310500 USD Yearly USD 153500.00 310500.00 YEAR
Job Description & How to Apply Below

Hewlett Packard Enterprise is seeking a Senior Design Verification Engineer to advance emulation-based verification for complex digital designs. You will define verification plans, build robust UVM/testbench environments, and drive coverage to closure in a hybrid work model with ~2 days in the office in Sunnyvale, CA.

The role requires 5–8 years in design verification, System Verilog/UVM expertise, and hands-on emulation experience (Cadence Palladium, Synopsys ZeBu, Mentor Veloce).

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Position Requirements
10+ Years work experience
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