Physical Design Flow and Methodology Engineer

Staff Physical Design Flow and Methodology Engineer

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the Chip Innovation Infrastructure team to engineer the future of ASIC design at Google.

You will own the development of cutting-edge flows, methodologies, and data management systems for physical design EDA tools operating within the Google Compute Engine environment. This role is a core catalyst: you will survey industry trends, perform technical evaluations, and implement best practices to streamline RTL-to-GDS workflows, dramatically increasing the efficiency of our physical design engineers and ensuring the high quality of results for all ASIC tapeouts.

You will have deep experience with industry-standard physical design tools and a solid command of common scripting languages.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits.